Calibration of gain and timing mismatch for TI-ADCs with signals in all Nyquist zones using adaptive noise canceller
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https://doi.org/10.54939/1859-1043.j.mst.77.2022.137-149Keywords:
All-digital feed-forward calibration; Sub-sampling TIADCs; FPGA implementation; ANC principle.Abstract
This paper presents a novel all-digital background calibration technique for general Time-Interleaved Analog-to-Digital Converters (TIADCs). Calibration of gain and timing mismatch of TIADCs using the estimation technique is designed based on the principle of the Adaptive Noise Canceller (ANC). In this ANC, there are two stages in gain, timing mismatch estimation in which a cascade structure of the correction and estimation is proposed to guarantee that our calibration achieves high performance. Besides the first Nyquit zone, the input signal at different Nyquist zones is also experimented. It is shown through the result that our calibration performs excellently on all chosen Nyquist zones. It achieves the SNDR (Signal to Noise Ratio) and SFDR (Spurious Free Dynamic Range) improvement of 19dB and 49dB, respectively. Moreover, the synthesized design with hardware co-simulation carried on the Xilinx Kintex-7 field-programmable gate array (FPGA) platform consumes only 7.36 % of the hardware resources of the FPGA chip and reduces the mismatch tone level to -87 dB. In addition, our convergence speed of SNDR during calibration is approximately 1/3 others.
References
[1] . H. L. Duc et al.,“Fully digital feed forward background calibration of clock skews for sub-sampling tiadcs using the polyphase decomposition,” IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 64, No. 6 (2017), pp. 1515–1528.
[2] . B. Razavi, “Design Considerations for Interleaved ADCs,” IEEE Journal of Solid-State Circuits, Vol. 48, No. 8 (2013), pp. 1806–1817.
[3] . J. G. Proakis and D. G. Manolakis, “Digital Signal Processing: Principles, Algorithms and Applications,” Upper Saddle River, New Jersey (2007).
[4] . P. Diniz, “Adaptive Filtering: Algorithms and Practical Implementation,” Kluwer international series in engineering and computer science, Springer (2008).
[5] . H. Le Duc et al., “A Fully Digital Background Calibration of Timing Skew in Undersampling TI-ADC,” IEEE 12th International in New Circuits and Systems Conference (NEWCAS) (2014).
[6] . D. Camarero et al., “Mixed-Signal Clock-Skew Calibration Technique for Time-Interleaved ADCs,” IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 55, No. 11 (2008), pp. 3676–3687.
[7] . A. Haftbaradaran and K. W. Martin, “A sample-time error compensation technique for time-interleaved adc systems,” IEEE in Custom Integrated Circuits Conference (CICC) (2007), pp. 341–344.
[8] . H. Le Duc et al., “All-Digital Calibration of Timing Skews for TIADCs Using the Polyphase Decomposition,” IEEE Transactions on Circuitsand Systems II: Express Briefs, Vol. 63 (2016).
[9] . J. Matsuno et al., “All-Digital Background Calibration Technique for Time-Interleaved ADC Using Pseudo Aliasing Signal,” IEEE Transactions on Circuits andSystems I: Regular Papers, Vol. 60, No. 5 (2013), pp.1113–1121.
[10] . P. Satarzadeh et al., “A parametric polyphase domain approach to blind calibration of timing mismatches for M-channel time-interleaved ADCs,” Proceedings of 2010 IEEE International Symposium on Circuits and Systems (ISCAS), (2010), pp. 4053–4056.
[11] . V. Divi and G. W. Wornell, “Blind Calibration of Timing Skew in Time-Interleaved Analog-to-Digital Converters,” IEEE Journal of Selected Topics in Signal Processing, Vol. 3, No. 3 (2009), pp. 509–522.
[12] . S. Huang and B. Levy, “Blind Calibration of Timing Offsets for Four-Channel Time-Interleaved ADCs,” IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 54, No. 4 (2007), pp. 863–876.
[13] . Le Duc Han, Thi Kim Phuong Dinh, Van-Phuc Hoang, and Duc Minh Nguyen. “All-digital background calibration of gain and timing mismatches in time-interleaved ADCs using adaptive noise canceller,” AEU-International Journal of Electronics and Communications 114 (2020): 152999.
[14] . J. A. McNeill et al., “Split ADC’ Calibration for All-Digital Correction of Time-Interleaved ADC Errors,” IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 56, No. 5 (2009), pp. 344–348,.
[15] . C. Vogel et al., “Adaptive blind compensation of gain and timing mismatches in M-channel time-interleaved ADCs,” 15th IEEE International Conference on Electronics, Circuits and Systems ICECS (2008), pp. 49–52.
[16] . S. Chenet al., “All-digital calibration of timing mismatch error in time-interleaved analog-to-digital converters,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 25, No. 9 (2017), pp. 2552–2560.
[17] . P. P. Vaidyanathan, “Multirate Systems and Filter Banks,” Upper Saddle River, NJ, USA:Prentice-Hall, Inc.(1993).
