Parallel encoding and decoding algorithms with optimized hardware architecture for polar codes to reduce complexity and processing time
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https://doi.org/10.54939/1859-1043.j.mst.102.2025.51-59Keywords:
Polar codes; Parallel encoding and decoding; Optimized hardware architecture.Abstract
This paper presents the development of a simplified equivalent algorithm for fully parallel encoding and decoding of polar codes, which reduces computational complexity and minimizes processing latency compared to existing parallel encoding and decoding methods. The algorithm is implemented in the System Generator/Vitis Model Composer with parameterization capabilities, enabling easy maintenance and adaptation of FPGA designs for future standards. The design accuracy is validated through MATLAB simulations of the standard 3GPP code, and RTL synthesis using Vivado significantly improves latency and throughput.
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