A design strategy for analyzing signal integrity in DDR3 bus of high speed embedded systems

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Authors

  • Nguyen Manh Hung (Corresponding Author) Institute of Electronics, Academy of Military Science and Technology
  • Phan Van Viet Institute of Electronics, Academy of Military Science and Technology
  • Pham Minh Thang Institute of Electronics, Academy of Military Science and Technology
  • Nguyen Van Khoi Institute of Electronics, Academy of Military Science and Technology

DOI:

https://doi.org/10.54939/1859-1043.j.mst.CAPITI.2024.75-81

Keywords:

Signal Integrity; PCB; DDR3; Trace Impedance.

Abstract

A complex modern embedded system using a multi-core Central Processing Unit (CPU) toward a compact integrated design in a single Printed Circuit Board (PCB). One of the biggest challenges of the design is to meet the Signal Integrity for high speed Double Data Rate 3 Synchronous Dynamic Random-Access Memory (DDR3) bus. A typical strategy to solve the challenge is the simulation on the computer, but this is not always an effective solution as has a gap between simulation software and practical PCB. The gap is correlated to localized changes in copper density within the PCB and characterization of heterogeneous materials in PCB that could lead to differences in the real PCB. The purpose of the research presents an analysis methodology to design DDR) memory interfaces in high speed embedded systems, related to Signal Integrity and the impact of copper density on PCB trace impedances to overcome these challenges. Moreover, the presented design methodology is also applied to the next generation DDR as well as other styles of CPU.

References

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Published

01-04-2024

How to Cite

Nguyen Manh Hung, Phan Van Viet, Pham Minh Thang, and Nguyen Van Khoi. “A Design Strategy for Analyzing Signal Integrity in DDR3 Bus of High Speed Embedded Systems”. Journal of Military Science and Technology, no. CAPITI, Apr. 2024, pp. 75-81, doi:10.54939/1859-1043.j.mst.CAPITI.2024.75-81.

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