Design and evaluation of sphere decoder accelerator on reconfiguration hardware
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https://doi.org/10.54939/1859-1043.j.mst.80.2022.80-91Keywords:
MIMO; FPGA; SM; SD; ML.Abstract
The Maximum likelihood (ML) detection can achieve the best bit error rate but requires very high computational complexity. The latter makes this algorithm is not practically applicable. Many decoder architectures hence have been proposed to overcome the ML high complexity. The sphere decoding (SD) algorithm is one of the most promising approaches that offer quasi-ML performance with a reasonable computing workload. This paper proposes an efficient and practical approach for a sphere decoder design on reconfigurable hardware (FPGA). The design is evaluated to yield a quality approximation of the Maximum Likelihood (ML) method but with significantly reduced computational complexity.
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