IMPLEMENTATION OF SOME DECODING ALGORITHMS FOR NB-LDPC CODES ON FPGA

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Abstract

Non-binary low-density parity-check codes (NB-LDPC) provide better error correction performance in comparison with their counterparts. However, the NB-LDPC decoder has a very high complexity, especially the processing of the check node unit. This paper evaluates the error correction performance of some decoding algorithms for NB-LDPC codes in different fields with different codeword lengths. The paper also presents the results of the implementation a decoder structure for the NB-LDPC (35,23) over GF(8) on the Spartan 6 board. Analysis and evaluation results show that decoding quality on hardware is equivalent to simulation results on software, demonstrating high feasibility in implementing decoder on a hardware platform, capable of application in devices of the advanced communication systems or high-speed read-and-write data storages.