Research on solutions to accelerate computation for CNN executed on resource-limited SoC-FPGA
DOI:
https://doi.org/10.54939/1859-1043.j.mst.CSCE9.2025.42-50Keywords:
Soc-FPGA; CNN; Classification.Abstract
This paper presents a method for designing and implementing an image recognition model on a System on Chip (SoC) platform integrated with Field Programmable Gate Arrays (FPGA). With the increasing demands for low-latency inference processing in edge computing and high energy efficiency, customized hardware acceleration solutions become essential. The embedded execution results of the model on the FPGA hardware of the SoC are compared with the PyTorch model running on the same resource-limited FPGA hardware, showing that this architecture provides a high-performance, low-latency solution, and demonstrates the feasibility of using Vitis High-Level Synthesis (HLS) to quickly generate specialized IP cores for edge computing applications. The results will serve as a solid foundation for continuing to build more complex network models for larger problems.
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