PHAN HONG MINH; NGUYEN TIEN VIET; DO DOANH DIEN. Hardware-efficient matrix multiplication core optimization for edge AI on FPGA. Journal of Military Science and Technology, [S. l.], n. IITE, p. 123–130, 2025. DOI: 10.54939/1859-1043.j.mst.IITE.2025.123-130. Disponível em: https://online.jmst.info/index.php/jmst/article/view/1869. Acesso em: 20 nov. 2025.